1. Field of Invention
This invention relates, in general, to means and methods for improved semiconductor devices and integrated circuits, and more particularly, to an improved self-aligned manufacturing process which is especially useful for dielectrically, (e.g. oxide) isolated structures, and to devices and circuits made thereby.
2. Background Art
Semiconductor devices and integrated circuits (IC's) are commonly made by creating a variety of doped regions in a semiconductor wafer substrate. The lateral geometry and position of the doped regions are fixed by successive masking operations. Each new mask layer must be aligned with the pattern created by the prior mask layer so that the device regions being added will register with those already in place. Since the alignment process is not perfect, some space is wasted in providing the needed alignment tolerance. This wasted space is increasingly important as the minimum dimensions of the device or IC structure shrink. It is common now to utilize device and circuit features whose minimum dimensions are of the order of 1-2 microns or less. When the alignment tolerance is even a fraction of a micron, substantial space is wasted.
This problem is particularly severe with dielectrically isolated devices and circuits. In these structures, the active device regions are placed in an island of semiconductor material which is surrounded laterally by a thick dielectric region. The island and the dielectric region are typically formed in the same wafer substrate. The dielectric region reduces the parasitic capacity and coupling between adjacent devices and permits higher frequency and lower power operation to be achieved. For silicon bipolar devices, a thick thermal oxide region is often used to form the dielectric isolation. The active device regions must be aligned with respect to this isolation region. In the past, two or more separate masks have been used to do this, each one requiring extra space for the alignment tolerance. While past efforts to achieve self-aligned device structures, as exemplified by U.S. Pat. Nos. 3,560,278 and No. Re 30,282, have proved useful where metallized or doped device areas were required, they have not proved practical for self-aligned device structures involving oxide isolation regions or the like. This is because the prior art structures and methods have not been compatible with the processes required to form dielectric isolation regions or the like. To overcome this limitation, it has been necessary with the prior art, to use additional masking steps or additional processing steps and materials. These additional steps result in significantly lower manufacturing yields and higher costs. Thus, a need has continued to exist for an improved self-aligned manufacturing process for electronic devices and circuits, particularly, a self aligned process adapted to the manufacture of dielectrically isolated semiconductor structures.
Accordingly, it is an object of this invention to provide an improved process for manufacturing semiconductor and other solid state devices and integrated circuits wherein a device region must be laterally self-aligned with respect to a dielectric isolation region.
It is an additional object of this invention to provide an improved process for manufacturing dielectrically isolated devices and circuits having more compact lateral dimensions.
It is a further object of this invention to provide an improved process for manufacturing semiconductor devices and integrated circuits in which device regions, such as the emitter and the emitter, base, and/or collector contacts, can be positioned laterally within another device region and automatically aligned with respect to each other and to the other device region, particularly a dielectric isolation region.
It is an additional object of this invention to provide an improved process for manufacturing semiconductor devices and integrated circuits of more compact dimensions by eliminating the alignment tolerance presently required to position device regions, such as the emitters and the emitter, base, and/or collector contacts, within the active semiconductor region of, for example, a non-walled emitter dielectrically isolated structure.
It is a further object of the present invention to provide an improved manufacturing process for eemiconductor and other solid state devices and integrated circuits, wherein dielectric isolation regions are self-aligned with other device regions by means of multiple oxide and nitride layers, wherein these layers are arranged so as to conveniently permit selective etching using oxide attacking etchants and nitride attacking etchants, and wherein the process is compatible with the use of organic resists for patterning.
It is an additional object of the present invention to provide an improved manufacturing process for semiconductor and other solid state devices and integrated circuits which achieves the above objects without additional alignment steps or adverse effects on manufacturing yield.
It is a yet additional object of this invention to provide improved semiconductor and solid state devices and integrated circuits made by the process of this invention.